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hd404344r series/hd404394 series rev. 7.0 sept. 1999 description the hd404344r series and hd404394 series 4-bit microcomputers are products of the hmcs400 series, which is designed to make application systems compact while realizing higher performance and increasing program productivity. each microcomputer has an a/d converter, two timers and a serial interface. the hd404344r series includes the hd404344r with on-chip 4-kword rom, hd404342r with 2-kword rom, and hd404341r with 1-kword rom. the hd404394 series includes the hd404394 with on-chip 4-kword rom, hd404392 with 2-kword rom, and hd404391 with 1-kword rom. the hd4074344 and hd4074394 are the prom version ztat ? microcomputers. programs can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (the prom program specifications are the same as for the 27256.) ztat ? : zero turn around time ztat is a trademark of hitachi ltd. features input/output pins ? hd404344r series, hd4074344: 22 pins (10pins: large-current i/o pins) ? hd404394 series: 21 pins (3 pins: intermediate-voltage nmos open drain i/o; 5 pins: nmos open drain i/o with 15-ma high-current driver) two timer/counters ? one timer output ? one event counter input (with programmable edge detection) 8-bit clock-synchronous serial interface (1 channel) on-chip a/d converter ? hd404344r series, hd4074344: 8 bit 4 channel ? hd404394 series: 8 bit 3 channel (with v ref pin) built-in oscillator
hd404344r series/hd404394 series 2 ? hd404344r series ceramic oscillator, cr oscillation, external clock drive is also possible. ? hd404394 series, hd4074344 ceramic oscillator, external clock drive is also possible. five interrupt sources ? one by external source (with programmable edge detection) ? four by internal sources subroutine stack ? maximum 16 levels including interrupts two low-power dissipation modes ? standby mode ? stop mode one input signal to return from stop mode instruction cycle time ? 1 m s (f osc = 4 mhz)
hd404344r series/hd404394 series 3 type of products product name type hd404344r series * 1 hd404394 series rom (words) ram (digit) package mask rom hd404341rs hd404391s 1,024 256 dp-28s hd40c4341rs hd404342rs hd404392s 2,048 hd40c4342rs hd404344rs hd404394s 4,096 hd40c4344rs hd404341rfp hd404391fp 1,024 fp-28da hd40c4341rfp HD404342RFP hd404392fp 2,048 hd40c4342rfp hd404344rfp hd404394fp 4,096 hd40c4344rfp hd404341rft hd404391ft 1,024 fp-30d hd40c4341rft hd404342rft hd404392ft 2,048 hd40c4342rft hd404344rft hd404394ft 4,096 hd40c4344rft hcd404344r 4,096 chip * 3 * 4 hcd40c4344r ztat ? hd4074344s hd4074394s 4,096 dp-28s hd4074344fp hd4074394fp fp-28da hd4074344ft hd4074394ft fp-30d note: 1. the hd404344r series is available in a mask rom version only. 2. ztat ? chip shipment is not supprted. 3. the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404344r series/hd404394 series 4 list of functions mask rom item hd404341r hd404342r hd404344r hcd404344r hd40c4341r hd40c4342r hd40c4344r operating voltage (v) 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 instruction cycle time (typ.) 1 m s (f osc = 4.0 mhz) 1 m s (f osc = 4.0 mhz) 1 m s (f osc = 4.0 mhz) 1 m s (f osc = 4.0 mhz) 2 m s (r f = 20 k w ) 2 m s (r f = 20 k w ) 2 m s (r f = 20 k w ) rom (words) 1,024 2.048 4,096 4,096 1,024 2,048 4,096 ram (digits) 256 256 256 256 256 256 256 i/o 22 22 22 22 22 22 22 high-current i/o pins (sink 15 ma max) 10 10 10 10 10 10 10 timer functions free running timer 22222 22 reload timer 22222 22 event counter 11111 11 watchdog timer 11111 11 serial interface 11111 11 a/d converter 8bit 4ch 8bit 4ch 8bit 4ch 8bit 4ch 8bit 4ch 8bit 4ch 8bit 4ch interrupt external 11111 11 internal 44444 44 low-power modes 22222 22 stop mode lllll ll standby mode lllll ll oscillator ceramic oscillation llll rc oscillation lll package dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d chip dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d guaranteed operation temperature ( c) ?0 to +75 ?0 to +75 ?0 to +75 +75 ?0 to +75 ?0 to +75 ?0 to +75
hd404344r series/hd404394 series 5 list of functions (cont) mask rom ztat ? item hcd40c4344r hd4074344 operating voltage (v) 2.7 to 5.5 2.7 to 5.5 instruction cycle time (typ.) 2 m s (r f = 20 k w ) 1 m s (f osc = 4.0 mhz) rom (words) 4,096 4,096 prom ram (digits) 256 256 i/o 22 22 high-current i/o pins (sink 15 ma max) 10 10 timer functions free running timer 22 reload timer 2 2 event counter 1 1 watchdog timer 11 serial interface 1 1 a/d converter 8bit 4ch 8bit 4ch interrupt external 1 1 internal 4 4 low-power modes 2 2 stop mode ll standby mode ll oscillator ceramic oscillation l rc oscillation l package chip dp-28s fp-28da fp-30d guaranteed operation temperature ( c) +75 ?0 to +75
hd404344r series/hd404394 series 6 list of functions (cont) mask rom ztat ? item hd404391 hd404392 hd404394 hd4074394 operating voltage (v) 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 instruction cycle time (typ.) 1 m s (f osc = 4.0 mhz) 1 m s (f osc = 4.0 mhz) 1 m s (f osc = 4.0 mhz) 1 m s (f osc = 4.0 mhz) rom (words) 1,024 2.048 4,096 4,096 prom ram (digits) 256 256 256 256 i/o 21 21 21 21 intermediate- voltage nmos open drain i/o 3333 nmos open drain i/o (15 ma high current driver) 5555 timer functions free running timer 2222 reload timer 2222 event counter 1111 watchdog timer 1111 serial interface 1112 a/d converter 8bit 3ch 8bit 3ch 8bit 3ch 8bit 3ch interrupt external 1111 internal 4444 low-power modes 2222 stop mode llll standby mode llll oscillator ceramic oscillation llll package dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d dp-28s fp-28da fp-30d guaranteed operation temperature ( c) ?0 to +75 ?0 to +75 ?0 to +75 ?0 to +75
hd404344r series/hd404394 series 7 pin arrangement hd404344r series, hd4074344 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 osc 1 osc 2 gnd r3 0 /an 0 r3 1 /an 1 2 /an 2 d 5 d 4 / stopc d 3 d 2 d 1 d 0 / int 0 /evnb r0 3 /toc r0 2 /so r0 1 /si r0 0 / sck reset test/v pp v cc r3 3 /an 3 dp-28s fp-28da 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 osc 1 osc 2 gnd nc r3 0 /an 0 r3 1 /an 1 2 /an 2 d 5 d 4 / stopc d 3 d 2 d 1 d 0 / int 0 /evnb r0 3 /toc r0 2 /so r0 1 /si r0 0 / sck reset test/v pp v cc nc r3 3 /an 3 fp-30d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 top view r3 r3 hd404394 series r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 osc 1 osc 2 v ref r3 1 /an 1 2 /an 2 d 5 d 4 / stopc d 3 d 2 d 1 d 0 / int 0 /evnb r0 3 /toc r0 2 /so r0 1 /si r0 0 / sck reset test/v pp v cc r3 3 /an 3 dp-28s fp-28da 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 osc 1 osc 2 gnd nc v ref r3 1 /an 1 2 /an 2 d 5 d 4 / stopc d 3 d 2 d 1 d 0 / int 0 /evnb r0 3 /toc r0 2 /so r0 1 /si r0 0 / sck reset test/v pp v cc nc r3 3 /an 3 fp-30d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 top view r3 gnd r3
hd404344r series/hd404394 series 8 pad arrangement hcd404344r, hcd40c4344r 30 type code type code: hd404344r (hcd404344r) hd40c4344r (hcd40c4344r) 29 28 24 1 23 22 21 27 26 25 10 11 12 14 15 16 13 2 3 4 5 6 7 20 19 18 17 8 9
hd404344r series/hd404394 series 9 bonding pad coordinates hcd404344r, hcd40c4344r type code chip size (x y): 3.23 3.65 (mm) coordinates: pad center home point position: chip center pad size (x y): 90 90 ( m) chip thickness: 400 ( m) chip center (x=0, y=0) pad coordinates pad coordinates no. pad name x ( m m) y ( m m) no. pad name x ( m m) y ( m m) 1 r13 ?425 1370 16 test 1360 ?627 2 r20 ?425 1050 17 reset 1418 ?456 3 r21 ?425 732 18 r00 1418 ?072 4 r22 ?425 455 19 r01 1418 ?90 5 r23 ?425 165 20 r02 1418 ?06 6 osc1 ?425 ?15 21 r03 1418 312 7 osc2 ?425 ?32 22 d0 1418 694 8 gnd ?425 ?97 23 d1 1418 1098 9 gnd ?425 ?244 24 d2 1418 1501 10 r30 ?257 ?627 25 d3 1075 1627 11 r31 ?91 ?627 26 d4 693 1627 12 r32 ?26 ?627 27 d5 309 1627 13 r33 ?62 ?627 28 r10 ?29 1627 14 v cc 420 ?627 29 r11 ?32 1627 15 v cc 804 ?627 30 r12 ?135 1627
hd404344r series/hd404394 series 10 pin description hd404344r series, hd4074344 pin number item symbol dp-28s/ fp-28da fp-30d chip i/o function power supply v cc 16 18 14, 15 applies power voltage gnd 11 11 8, 9 connects to ground test test 17 19 16 i cannot be used in user applications. connect this pin to gnd. reset reset 18 20 17 i resets the mcu oscillator osc 1 9 9 6 i input/output pins for the internal oscillator. connect these pins to the ceramic oscillator, or osc 1 to an external oscillator circuit. osc 2 10 10 7 o port d 0 ? 5 23?8 25?0 22?7 i/o input/output pins addressed individually by bits; pins d 1 and d 2 can sink 15 ma max. r0 0 ?0 3 , r1 0 ?1 3 , r2 0 ?2 3 , r3 0 ?3 3 1?, 12?5 19?2 1?, 13?6, 21?4 18?1, 28?0, 1?, 10?3 i/o four-bit input/output pins. pins r1 0 ?2 3 can sink 15 ma max. interrupt int 0 23 25 22 i input pin for external interrupts stop clear stopc 27 29 26 i input pin for transition from stop mode to active mode serial interface sck 19 21 18 i/o serial interface clock input/output pin si 20 22 19 i serial interface receive data input pin so 21 23 20 o serial interface transmit data output pin timer toc 22 24 21 o timer output pin evnb 23 25 22 i event count input pin a/d converter an 0 ?n 3 12?5 13?6 10?3 i analog input pins for the a/d converter
hd404344r series/hd404394 series 11 hd404394 series pin number item symbol dp-28s/ fp-28da fp-30d i/o function power supply v cc 16 18 applies power voltage gnd 11 11 connects to ground test test 17 19 i cannot be used in user applications. connect this pin to gnd. reset reset 18 20 i resets the mcu oscillator osc 1 9 9 i input/output pin for the internal oscillator. connect these pins to the ceramic oscillator, or osc 1 to an external oscillator circuit osc 2 10 10 o port d 0 ? 5 23?8 25?0 i/o input/output pins addressed individually by bits; pins d 1 and d 2 can sink 15 ma max. r0 0 ?0 3 , r1 0 ?1 3 , r2 0 ?2 3 , r3 1 ?3 3 1?, 13?5 19?2 1?, 14?6, 21?4 i/o four-bit input/output pins. pins r1 0 ?1 2 are nmos intermediate-voltage open drain pins. pins r1 3 ?2 3 are nmos standard-voltage open drain pins which can sink 15 ma max. interrupt int 0 23 25 i input pin for external interrupts stop clear stopc 27 29 i input pin for transition from stop mode to active mode serial interface sck 19 21 i/o serial interface clock input/output pin si 20 22 i serial interface receive data input pin so 21 23 o serial interface transmit data output pin timer toc 22 24 o timer output pin evnb 23 25 i event count input pin a/d converter v ref 12 13 power supply for the internal ladder resistor in the a/d converter an 1 ?n 3 13?5 14?6 i analog input pins for the a/d converter
hd404344r series/hd404394 series 12 hd404344r series, hd4074344 block diagram d 0 d 1 d 2 d 3 d 4 d 5 r0 0 d port r0 port rom (1,024 10 bits) (2,048 10 bits) (4,096 10 bits) pc (14 bits) instruction decoder sp (10 bits) b (4 bits) a (4 bits) st (1 bit) ca (1 bit) alu spy (4 bits) y (4 bits) spx (4 bits) x (4 bits) w (2 bits) ram (256 4 bits) system control interrupt control timer b timer c serial interface a/d converter internal data bus internal data bus internal address bus an 0 an 1 si so sck toc evnb int 0 data bus large-current pin bidirectional signal line gnd v cc osc 2 osc 1 stopc test reset an 2 an 3 r0 1 r0 2 r0 3 r3 0 r3 port r3 1 r3 2 r3 3 r1 0 r1 port r1 1 r1 2 r1 3 r2 0 r2 port r2 1 r2 2 r2 3
hd404344r series/hd404394 series 13 hd404394 series block diagram d 0 d 1 d 2 d 3 d 4 d 5 r0 0 d port r0 port rom (1,024 10 bits) (2,048 10 bits) (4,096 10 bits) pc (14 bits) instruction decoder sp (10 bits) b (4 bits) a (4 bits) st (1 bit) ca (1 bit) alu spy (4 bits) y (4 bits) spx (4 bits) x (4 bits) w (2 bits) ram (256 4 bits) system control interrupt control timer b timer c serial interface a/d converter internal data bus internal data bus internal address bus an 1 an 2 si so sck toc evnb int 0 data bus large-current pin bidirectional signal line gnd v cc osc 2 osc 1 stopc test reset an 3 v ref r0 1 r0 2 r0 3 r3 port r3 1 r3 2 r3 3 r1 0 r1 port r1 1 r1 2 r1 3 r2 0 r2 port r2 1 r2 2 r2 3 intermediate- voltage nmos open drain pins standard- voltage nmos open drain pins
hd404344r series/hd404394 series 14 memory map rom memory map the rom memory map for the mcu is shown in figure 1 and explained as follows. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 jmpl instruction (jump to reset , stopc routine) jmpl instruction (jump to int routine) 0 not used jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to a/d converter routine) jmpl instruction (jump to serial routine) vector address zero-page subroutine (64 words) hd404341r, hd40c4341r, hd404391 program/pattern (1,024 words) not used hd404342r, hd40c4342r, hd404392 program/pattern (2,048 words) hd404344r, hd40c4344r, hcd404344r, hcd40c4344r,hd404394, hd4074344, hd4074394 program/pattern (4,096 words) $0000 $000f $0010 $03ff $0400 $0fff $1000 $3fff $003f $0040 $07ff $0800 0 15 16 63 64 1023 1024 4095 4096 16383 2047 2048 figure 1 rom memory map
hd404344r series/hd404394 series 15 vector address area ($0000 to $000f): when an mcu reset or an interrupt process is executed, the program will begin executing from a vector address. the jmpl instructions which branch to the reset routine and interrupt routine should be programmed at these top addresses. zero-page subroutine area ($0000?003f): this area is reserved for subroutines. the program branches to a subroutine in this area in response to a cal instruction. pattern area: hd404341r, hd40c4341r, hd404391?0000 to $03ff hd404342r, hd40c4342r, hd404392?0000 to $07ff hd404344r, hd40c4344r, hcd404344r, hcd40c4344r, hd404394, hd4074344, hd4074394 $0000 to $0fff this area contains rom data which can be referenced with the p instruction. program area: hd404341r, hd40c4341r, hd404391?0000 to $03ff hd404342r, hd40c4342r, hd404392?0000 to $07ff hd404344r, hd40c4344r, hcd404344r, hcd40c4344r, hd404394, hd4074344, hd4074394 $0000 to $0fff
hd404344r series/hd404394 series 16 ram memory map the mcu ram contains 256 digits 4 bits which is used for the memory registers, and the data and stack areas. the interrupt control bits area, special register area, and the register flag area are mapped into the ram memory. the ram memory area is shown in figure 2 and explained as follows. a/d channel register (acr) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $033 $00a $00b $00e $00f w w r/w w w w w w w w w w r r r r r/w r/w r/w r/w r/w $3c0 ram-mapped registers memory registers (mr) stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register (smr) serial data register lower (srl) serial data register upper (sru) timer mode register b1 (tmb1) timer b (trbl/twbl) (trbu/twbu) miscellaneous register (mis) timer mode register c (tmc) timer c (trcl/twcl) (trcu/twcu) register flag area port r0 dcr (dcr0) port r3 dcr (dcr3) not used * two registers are mapped on the same area ($00a, $00b, $00e, $00f). timer read register b lower (trbl) timer read register b upper (trbu) timer read register c lower (trcl) timer read register c upper (trcu) timer write register b lower (twbl) timer write register b upper (twbu) timer write register c lower (twcl) timer write register c upper (twcu) r: read only w: write only r/w: read/write note: $016 r a/d data register lower (adrl) $017 $018 $019 $01a $3ff a/d data register upper (adru) a/d mode register 1 (amr1) a/d mode register 2 (amr2) r w w w port mode register b (pmrb) port mode register c (pmrc) timer mode register b2 (tmb2) not used w w w $030 data (176 digits) not used not used * $03f not used $100 not used w w port r1 dcr (dcr1) port r2 dcr (dcr2) $031 $032 w port d 4 , d 5 dcr w port d 0 ? 3 dcr $020 $023 $024 $025 $026 $02d $02c not used (dcd0) (dcd1) figure 2 ram memory map
hd404344r series/hd404394 series 17 ram map register area ($000 to $03f): interrupt control bits area: $000 to $003 this area is made up of bits used for interrupt control as shown in figure 3. each bit can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). some bits however, have limitations along with certain instructions as shown in figure 4. special register area: $004 to $01f, $024 to $03f this area is made up of mode registers and data registers, such as for external interrupt, serial interface, timers, a/d converter, and data control for the i/o ports. its configurations are shown in figures 2 and 5. these registers are categorized as write-only, read-only, and write/read. they can not be accessed by ram bit manipulation instructions. register flag area: $020 to $023 this area is used for the wdon flag and other interrupt control flags. its configuration is shown in figure 3. each bit can be accessed only by the sem/semd, rem/remd, and tm/tmd instructions. some bits however, have limitations along with certain instructions as shown in figure 4. data area ($040 to $0ff): sixteen of the 176 digits in this area, from $040 to $04f, are memory registers. these registers can be accessed by the lamr and xmra instructions. its configuration is shown in figure 6. stack area ($3c0 to $3ff): this area is used to hold the program counter (pc), the status flag (st), and the carry flag (ca) for subroutine calls (cal and call instructions) and interrupts. since four digits are used for each level, this area can be used for stacking up to 16 subroutines. the stacking order of saved data and the storing of bits are shown in figure 6. the program counter is recovered by the rtn and rtni instructions. the status and carry flags are recovered only by the rtni instruction. any area not used in the stack area is available for data storage.
hd404344r series/hd404394 series 18 bit 3 bit 2 bit 1 bit 0 imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) ims (im of serial) ifs (if of serial) imad (im of a/d) ifad (if of a/d) $0000 $0001 $0002 $0003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) $020 $021 $022 $023 register flag area adsf (a/d start flag) wdon (watchdog on flag) rame (ram enable flag) interrupt request flag interrupt mask interrupt enable flag sp: stack pointer bit 3 bit 2 bit 1 bit 0 ram address iaof (i ad off flag) : not used if: im: ie: figure 3 configuration of interrupt control bits and register flag areas sem/semd ? the wdon bit can be reset by an mcu reset or by stop mode release with stopc . ? do not use rem/remd for the adsf bit during a/d conversion. ? if the tm or tmd instruction is excuted for the inhibited or non-existing bits, the value in st becomes invaild. ie im iaof if rame rsp wdon adsf not used rem/remd tm/tmd can be used can be used can be used can be used can be used not processed inhibited to access not processed can be used not processed not processed can be used can be used not processed inhibited to access inhibited to access can be used inhibited to access figure 4 limitations for ram bit manipulation instructions
hd404344r series/hd404394 series 19 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f pmra smr srl sru tmb1 trbl/twbl trbu/twbu mis tmc trcl/twcl trcu/twcu acr adrl adru amr1 amr2 pmrb pmrc tmb2 dcd0 dcd1 dcr0 dcr1 dcr2 dcr3 bit 3 im0 imtc ims r0 0 / sck reload control pull-up control reload control r3 3 /an 3 rame d 4 /stopc d 3 dcr r0 3 dcr r1 3 dcr r2 3 dcr r3 3 dcr bit 2 if0 iftc ifs r0 3 /toc so pmos control r3 2 /an 2 adsf iaof d 2 dcr r0 2 dcr r1 2 dcr r2 2 dcr r3 2 dcr bit 1 rsp imtb imad r0 1 /si r3 1 /an 1 wdon so idle level d 1 dcr d 5 dcr r0 1 dcr r1 1 dcr r2 1 dcr r3 1 dcr bit 0 ie iftb ifad r0 2 /so r3 0 /an 0 * a/d conversion speed d 0 / int 0 /evnb transmit clock d 0 dcr d 4 dcr r0 0 dcr r1 0 dcr r2 0 dcr register name serial data transfer speed serial data register (lower) serial data register (upper) timer b clock source timer b register (lower) timer b register (upper) timer c clock source timer c register (lower) timer c register (upper) a/d channel selection a/d data register (lower) a/d data register (upper) evnb edge detection : not used note: * applies to the hd404344r series and hd4074344. does not apply to the hd404394 series. r3 0 dcr * figure 5 special register area
hd404344r series/hd404394 series 20 memory registers $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f $3c0 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 pc ?c : st: ca: program counter 13 stack area 0 $3fc $3fd $3fe $3ff status flag carry flag note: since hd404344r series, hd4074344 and hd404394 series have a 4-kword rom, pc 12 and pc 13 are ignored. figure 6 configuration of memory registers, stack area, and stack position
hd404344r series/hd404394 series 21 functional description registers and flags the cpu has nine registers and two flags. their configurations are shown in figure 7 and explained as follows. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 7 registers and flags
hd404344r series/hd404394 series 22 accumulator (a), b register (b): the accumulator and b register are 4-bit registers used for storing alu operation results and data that is transferred between memory and i/o ports or between other registers. w register (w), x register (x), y register (y): the w register is a 2-bit register and the x and y registers are 4-bit registers. these are used for indirect addressing to ram. the y register is also used for addressing the d port. spx register (spx), spy register (spy): the spx and spy registers are 4-bit registers that supplement the x and y registers, respectively. carry flag (ca): the carry flag latches the alu overflow during an arithmetic instruction execution. it is controlled by the sec, rec, rotl, and rotr instructions. the carry flag is stored during interrupt processing, then recovered from the stack by a rtni instruction. (it is not affected by the rtn instruction.) status flag (st): the status flag latches the overflow of alu arithmetic instructions and compara tive instructions, and also the results of alu non-zero and bit test instructions. it is then used for branch conditions of the br, brl, cal, and call instructions. the status flag remains unchanged until the next arithmetic instruction, comparative instruction, or bit test is executed. after a br, brl, cal, or call instruction is executed, the status flag will be set to 1 regardless if the instruction is executed or skipped. the contents of the status flag is stored on the stack during interrupt processing, then recovered from the stack by a rtni instruction. program counter (pc): this 14-bit binary counter maintains rom address information. stack pointer (sp): the stack pointer is a 10-bit register which contains the address of the next stack space to be used. it is initialized as $3ff by an mcu reset. when data is stored onto the stack, the sp is decremented by 4, and when data is pulled from the stack, it is incremented by 4. the top four bits of the stack pointer are fixed at 1111, so it can be used for a maximum of 16 levels. there are two ways of initializing the stack pointer to $3ff. one is by mcu reset and the other is by resetting the rsp bit with a rem or a remd instruction. reset an mcu reset is executed by setting reset low. the reset input must be more than t rc so as to keep the oscillator steady during power on or when stop mode is cancelled. for other cases, the mcu can be reset by a reset input for a minimum of two instruction cycle times. initialized values by mcu reset are listed in table 1. certain bits in the interrupt control bits area and the register flag area can be set or reset by the sem/semd or rem/remd instructions. also these can be tested by the tm/tmd instruction. the following specifies the limitations for each bit.
hd404344r series/hd404394 series 23 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0, dcd1) all bits 0 turns output buffer off (to high impedance) (dcr0,- dcr3) all bits 0 port mode register a (pmra) - 000 refer to description of port mode register a port mode register b (pmrb) 0 - - 0 refer to description of port mode register b port mode register c (pmrc) - - - 0 refer to description of port mode register c timer/ counters, serial interface timer mode register b1 (tmb1) 0000 refer to description of timer mode register b1 timer mode register b2 (tmb2) - - 00 refer to description of timer mode register b2 timer mode register c (tmc) 0000 refer to description of timer mode register c serial mode register (smr) 0000 refer to description of serial mode register prescaler s (pss) $000 timer counter b (tcb) $00 timer counter c (tcc) $00 timer write register b (twbu, twbl) $x0 timer write register c (twcu, twcl) $x0 octal counter 000
hd404344r series/hd404394 series 24 table 1 initial values after mcu reset (cont) item abbr. initial value contents a/d a/d mode register 1 (amr1) 0000 refer to description of a/d mode register a/d mode register 2 (amr2) - - - 0 refer to description of a/d mode register bit register watchdog timer on flag (wdon) 0 refer to description of timer c a/d start flag (adsf) 0 refer to description of a/d converter i ad off flag (iaof) 0 refer to description of a/d converter others miscellaneous register (mis) 00 - - refer to description of i/o, and serial interface notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist. table 1 initial values after mcu reset (cont) after stop mode release by stopc input after stop mode release by reset input after other types of mcu reset carry (ca) program needs to initialize these registers. program needs to initialize these registers. accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (sru, srl) a/d data register (adru, adrl) ram data before entering stop mode are kept. ram enable flag (rame) 1 0 0 port mode register b bit 3 (pmrb3) data before entering stop mode are kept. 00
hd404344r series/hd404394 series 25 interrupts there are five kinds of interrupts: external int 0 , timer b, timer c, serial interface, and a/d converter. an interrupt request flag or an interrupt mask and vector address are used for each type of interrupt. they are used for storing interrupt requests and interrupt controls. an interrupt enable flag is also used for total interrupt control. interrupt control bits and interrupt processing: the interrupt control bits are mapped from $000 to $003 of ram and can be accessed by ram bit manipulation instructions. however, the interrupt request flag (if) cannot be set by software. an mcu reset initializes the interrupt enable flag (ie) and the interrupt request flag (if) to 0, and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 8. the interrupt priority order and vector addresses are listed in a table in the figure, along with the conditions for executing the interrupt processing of the five types of interrupt requests (table 2). an interrupt request occurs when the interrupt request flag is set to 1 and the interrupt mask to 0. if the interrupt enable flag is 1, interrupt processing has occurred. the vector address which corresponds to the interrupt source is generated from the priority pla. the interrupt processing sequence is shown in figure 9 and the interrupt processing flowchart is shown in figure 10. after receiving an interrupt, the previous instruction is completed in the first cycle. the interrupt enable flag (ie) is reset after two cycles. the contents of the carry flag, status flag, and program counter are stored onto the stack at the second and third cycles. instruction execution is restarted by jumping to the vector address during the third cycle. the jmpl instructions, which branch to the start addresses of the interrupt routines, should be programmed at each vector address area. the interrupt request which initiated the interrupt processing should be reset by software instructions in the interrupt routine.
hd404344r series/hd404394 series 26 ie if0 im0 iftb imtb iftc imtc ifad imad $000,0 $000,2 $000,3 $002,0 $002,1 $002,2 $002,3 $003,0 $003,1 interrupt request priority controller ifs ims $003,2 $003,3 int 0 interrupt timer b interrupt timer c interrupt a/d interrupt serial interrupt priority order vector address 1 2 3 4 5 $0000 $0002 $0008 $000a $000c $000e ( reset , stopc * ) note: * stopc interrupt request is enabled only when the mcu is in stop mode. figure 8 interrupt control circuit, vector addresses, and interrupt priorities
hd404344r series/hd404394 series 27 table 2 interrupt processing and activation conditions interrupt source interrupt control bit int 0 timer b timer c a/d serial ie 111 11 if0 im0 100 00 iftb imtb * 10 00 iftc ? imtc ** 100 ifad imad *** 10 ifs ims *** * 1 note: * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution * interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine stacking; vector address generation stacking; ie reset note: * the stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction. figure 9 interrupt processing sequence
hd404344r series/hd404394 series 28 power on reset = 0? reset mcu interrupt request? execute instruction pc ? (pc) + 1 pc ? $0002 pc ? $000a pc ? $000c pc ? $000e ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? timer c interrupt? a/d interrupt? no yes no yes no yes yes yes yes no no no no ? ? ? (serial interrupt) pc ? $0008 timer b interrupt? yes figure 10 interrupt processing flowchart
hd404344r series/hd404394 series 29 interrupt enable flag (ie: $000, bit 0): the interrupt enable flag executes interrupt enable/disable for all interrupt requests as listed in table 3. it is reset by interrupt processing and set by the rtni instruction. table 3 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupt ( int 0 ): int 0 input should be selected by using port mode register b (pmrb: $024), so that the external interrupt request flag (if0) is set at the falling edge of the int 0 input. external interrupt request flag (if0: $000, bit 2): the external interrupt request flag is set by the int 0 input edge, as listed in table 4. table 4 external interrupt request flag (if0: $000, bit 2) if0 interrupt request 0no 1 yes external interrupt mask (im0: $000, bit 3): im0 is a bit which masks the interrupt request caused by an external interrupt request flag, as listed in table 5. table 5 external interrupt mask (im0: $000, bit 3) im0 interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): the timer b interrupt request flag is set by the overflow output of timer b, as listed in table 6. table 6 timer b interrupt request flag (iftb: $002, bit 0) iftb interrupt request 0no 1 yes
hd404344r series/hd404394 series 30 timer b interrupt mask (imtb: $002, bit 1): imtb is a bit which masks the interrupt request caused by the timer b interrupt request flag, as listed in table 7. table 7 timer b interrupt mask (imtb: $002, bit 1) imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): the timer c interrupt request flag is set by the overflow output of timer c, as listed in table 8. table 8 timer c interrupt request flag (iftc: $002, bit 2) iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): imtc is a bit which masks the interrupt request caused by the timer c interrupt request flag, as listed in table 9. table 9 timer c interrupt mask (imtc: $002, bit 3) imtc interrupt request 0 enabled 1 disabled (masked) serial interrupt request flag (ifs: $003, bit 2): a serial interrupt request flag is set when the serial data transfer is completed or when the data transfer is suspended, as listed in table 10. table 10 serial interrupt request flag (ifs: $003 bit 2) ifs interrupt request 0no 1 yes
hd404344r series/hd404394 series 31 serial interrupt mask (ims1: $003, bit 3): ims1 is a bit which masks the interrupt request caused by the serial interrupt request flag, as listed in table 11. table 11 serial interrupt mask (ims: $003, bit 3) ims interrupt request 0 enabled 1 disabled (masked) a/d interrupt request flag (ifad: $003, bit 0): the a/d interrupt request flag is set after the a/d conversion is completed, as listed in table 12. table 12 a/d interrupt request flag (ifad: $003, bit 0) ifad interrupt request 0no 1 yes a/d interrupt mask (imad: $003, bit 1): imad is a bit which masks the interrupt request caused by the a/d interrupt request flag, as listed in table 13. table 13 a/d interrupt mask (imad: $003, bit 1) imad interrupt request 0 enabled 1 disabled (masked)
hd404344r series/hd404394 series 32 operating modes the mcu has three operating modes as shown in table 14. the transitions between the operating modes are shown in figure 11. table 14 operations in each operating mode function active mode standby mode stop mode system oscillator op op stopped cpu op retained reset ram op retained retained timers b, c op op reset serial op op reset a/d op op reset i/o op retained * reset notes: op implies in operation. * since input/output circuits are in operation, the current will flow in/out depending on the pin status in standby mode. note that this current is in addition to the standby mode dissipation current. active mode standby mode mcu reset stop mode reset = 1 reset = 0 reset = 0 reset = 0 stop instruction sby instruction interrupt request figure 11 mcu status transition
hd404344r series/hd404394 series 33 active mode: all functions operate in active mode. in active mode, the mcu is controlled by the oscillating circuit of osc 1 and osc 2 . standby mode: the mcu switches to standby mode when an sby instruction is executed. in standby mode, the oscillator continues operating, but the clocks related to instruction execution stops running. this causes the cpu to stop operating. however, the contents of ram are retained. also, the d and r ports, which are set as output, maintain their status before entering standby mode. the peripheral functions, such as interrupt, timers, serial interface, and a/d converter, continue operating. power dissipation in standby mode is less than in active mode because of the cpu not operating. the mcu enters standby mode when the sby instruction is executed in active mode. to terminate standby mode, provide a reset input or an interrupt request. if a reset input is given, the mcu will be reset. if an interrupt request is given, the mcu will change to active mode and the next instruction will be executed. after the instruction execution, if the interrupt enable flag is 1, the interrupt operation is executed. if the interrupt enable flag is 0, normal instruction execution continues and the interrupt request is left pending. the standby mode flowchart is shown in figure 13. stop mode: the mcu enters stop mode when a stop instruction is received. in stop mode, all mcu functions stop, except for maintaining ram data. power dissipation in this mode is therefore the lowest of all operating modes. in stop mode, the osc 1 and osc 2 oscillator is stopped. to terminate stop mode provide either a reset or stopc input as shown in figure 12. when terminating stop mode, it is important to ensure a proper oscillation stabilization period of at least t rc for the reset or stopc input. (refer to the ac characteristics tables.) after clearing stop mode, the ram maintains its data kept before entering stop mode. however, the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and the serial data register are not maintained. clearing stop mode using stopc : the mcu is transition from stop mode to active mode by either a reset or stopc input. the mcu starts instruction execution from the start of the program at address 0. then the ram enable flag (rame: $021, 3) is set accordingly, rame = 0 for reset input and rame = 1 for stopc input. a reset input is effective when the mcu is in any mode. a stopc input however, is effective only in stop mode and is ignored in other modes. so, when clearing stop mode with a stopc input the program needs to identify the rame status. (for example, when the ram contents before entering stop mode is used after transition to active mode.) a test instruction for the ram enable flag (rame) should be executed at the beginning of the program.
hd404344r series/hd404394 series 34 table 15 operating modes and transition conditions mode conditions to enter mode conditions to exit mode active mode reset release interrupt request stopc release in stop mode reset input stop/sby instruction standby mode sby instruction reset input interrupt request stop mode stop instruction reset input stopc input in stop mode stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset or stopc figure 12 timing of stop mode cancellation
hd404344r series/hd404394 series 35 standby oscillator: active peripheral clocks: active all other clocks: stop no yes no yes no yes no yes no yes no yes no yes reset = 0? if0 ? im0 = 1? iftb ? imtb = 1? iftc ? imtc = 1? ifad ? imad = 1? ifs ? ims = 1? stop oscillator: stop peripheral clocks: stop all other clocks: stop reset = 0? stopc = 0? yes yes no no restart processor clocks execute next instruction if = 1, im = 0, and ie = 1? interrupt accept execute next instruction reset mcu restart processor clocks rame = 0 rame = 1 figure 13 mcu process flowchart
hd404344r series/hd404394 series 36 mcu operation sequence: the mcu operates according to the flowcharts shown in figures 14 to 16. since reset is asynchronous input, the mcu will be reset in any mode that the mcu is operating in. the low-power mode operation sequence is shown in figure 16. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 0? rame = 0 reset mcu mcu operation cycle no yes figure 14 mcu operation sequence (power on)
hd404344r series/hd404394 series 37 if = 1? instruction execution sby/stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag mcu operation cycle figure 15 mcu operation sequence (mcu operation cycle)
hd404344r series/hd404394 series 38 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby mode (sby) if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes note: * for if and im operation, refer to figure 13. stopc = 0? rame = 1 reset mcu no yes * figure 16 mcu operation sequence (low power mode operation)
hd404344r series/hd404394 series 39 oscillator circuit figure 17 shows a block diagram of the clock generation circuit. ceramic oscillator can be connected to osc 1 and osc 2 as listed in table 16. an external clock can also be connected. in addition, the system oscillator of the hd404344r series is capable of cr oscillation. osc 2 osc 1 system oscillator 1/4 division circuit timing generator circuit system clock generation cpu with rom, ram, registers, flags, and i/o peripheral function interrupt f cyc t cyc f osc cpu per figure 17 clock generation circuit r2 3 osc 1 osc 2 gnd : gnd figure 18 typical layout of ceramic oscillator
hd404344r series/hd404394 series 40 table 16 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic oscillator gnd ceramic oscillator : csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: kbr-4.0msa (kyocera) r f = 1 m w 20% c 1 = c 2 = 33 pf 20% cr oscillation (osc 1 , osc 2 ) hd404344r series osc 2 osc 1 r f r f = 20 k w 1% notes: 1. since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , and elements should be as short as possible, and must not cross other wiring (see figure 18).
hd404344r series/hd404394 series 41 input/output the hd404344r series and hd4074344 mcu has 22 input/output pins (d 0 ? 5 , r0 0 ?3 3 ) and the hd404394 mcu has 21 input/output pins (d 0 ? 5 , r0 0 ?2 3 , r3 1 ?3 3 ). these input/output pins have the following features: all 22 pins for the hd404344r series and hd4074344 have a cmos output circuit. ten pins d 1 , d 2 , and r1 0 ?2 3 are large current input/output pins. three input/output pins of the 21 pins on the hd404394 series, r1 0 ?1 2 , have intermediate-voltage nmos open drain output circuits. five other input/output pins, r1 3 and r2 0 ?2 3 , have standard-voltage nmos open drain output circuits. the remaining 13 input/output pins, d 0 ? 5 , r0 0 ?0 3 and r3 1 ?3 3 , have cmos output circuits. ten pins d 1 , d 2 , and r1 0 ?2 3 are high-current input/output pins. some input/output pins are multiplexed with peripheral functions, such as for the timers and serial interface. for these pins, the settings for peripheral functions are done prior to the d or r ports settings. if these pins are set as peripheral functions, the pin functions and input/output selections automatically switch according to the settings. program control of input/output port selection, as well as peripheral function selection. all peripheral function output pins are cmos output pins. however, the r0 2 /so pin can be programmed to be nmos open drain output. in stop mode, all peripheral function selections are cleared because of the mcu being reset. also, the input/output pins go into a high-impedance state. all input/output pins for both the hd404344r series, hd4074344 and the hd404394 series except for pins r1 0 ?2 3 , have built-in pull-up mos. therefore they can be individually turned on or off by software. when pin functions are set as peripheral functions after selecting the pins as pull-up mos, the pins are maintained as pull-up mos from the time of selection. also, pull-up mos can be selected by software after setting the pin functions as peripheral functions. the control of the input/output pins are shown in table 17 and the circuit configuration of each input/output pin is shown in table 18. table 17 programmable control of standard i/o pins mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos onon note: ?indicates off.
hd404344r series/hd404394 series 42 table 18 circuit configurations of i/o pins pins i/o pin type circuit hd404344r series, hd4074344 hd404394 series input/output pins pull-up control signal v cc v cc input control signal input data output data buffer control signal hlt mis3 pdr dcd, dcr d 0 ? 5 , r0 0 , r0 1 r0 3 , r1 0 ?3 3 d 0 ? 5 , r0 0 , r0 1 r0 3 , r3 1 ?3 3 v cc v cc input control signal input data output data hlt pdr dcr buffer control signal none r1 3 , r2 0 ?2 3 (standard voltage pins) pull-up control signal v cc v cc input control signal input data output data buffer control signal hlt mis3 pdr dcr mis2 r0 2 r0 2 input control signal input data hlt pdr dcr none r1 0 ?1 2 (middle voltage pins)
hd404344r series/hd404394 series 43 table 18 circuit configurations of i/o pins (cont) pins i/o pin type circuit hd404344r series, hd4074344 hd404394 series peripheral function pins input/ output pins pull-up control signal v cc v cc input data output data hlt mis3 sck sck sck sck output pins pull-up control signal v cc v cc output data pmos control signal hlt mis3 so mis2 so so pull-up control signal v cc v cc output data hlt mis3 toc toc toc input pins si, int 0 , input data evnb, stopc v cc hlt pdr mis3 si, int 0 , evnb, stopc si, int 0 , evnb, stopc v cc hlt pdr mis3 a/d input input control an 0 ?n 3 an 1 ?n 3 note: in stop mode, the mcu is reset and the peripheral function selection is cancelled. also, the hlt signal goes low, and input/output pins enter a high-impedance state.
hd404344r series/hd404394 series 44 d port the d port consists of six input/output pins each addressed by one bit. the d ports can be set and reset by sed/red and sedd/redd instructions. output data is stored in the port data register (pdr) for each pin. also, all d ports can tested by the td/tdd instructions. the on/off status of the output buffers is controlled by the d-port data control registers (dcd0, dcd1: $02c and $02d), which are mapped to memory addresses (figure 19). pins d 0 and d 4 are multiplexed with peripheral function pins int 0 /evnb, and stopc . setting of the peripheral functions for these pins is executed by bits 3 and 0 (pmrb3, pmrb0) of port mode register b (pmrb: $024) (figure 20). bit initial value read/write bit name 3 0 w 2 0 w 0 0 w 1 0 w dcd0, dcd1 dcr0 to dcr3 data control register (dcd0, dcd1: $02c, $02d) (dcr0 to dcr3: $030 to $033) dcr00 to dcr30 dcr01 to dcr31 bits 0 to 3 0 cmos buffer control cmos buffer off (high impedance) cmos buffer on register dcd0 dcd1 dcr0 dcr1 dcr2 dcr3 bit 3 d ? r0 3 r1 3 r2 3 correspondence between ports and dcr bits bit 2 ? r0 2 r1 2 r2 2 r3 2 bit 1 d r0 1 r1 1 r2 1 r3 1 bit 0 d r0 0 r1 0 r2 0 r3 0 1 dcd01 to dcd11 dcd00 to dcd10 dd d r3 3 * note: * available for the hd404344r series and hd4074344, but not available for the hd404394 series. dcd03 dcd02 dcr02 to dcr32 dcr03 to dcr33 3210 54 figure 19 data control register (dcr)
hd404344r series/hd404394 series 45 bit initial value read/write bit name 3 0 w pmrb3 2 ? ? not used 0 0 w pmrb0 1 ? ? not used pmrb0 0 1 d 0 / int 0 /evnb mode selection d 0 int 0 port mode register b (pmrb: $024) pmrb3 0 1 d 4 / stopc mode selection d 4 stopc /evnb figure 20 port mode register b (pmrb)
hd404344r series/hd404394 series 46 r port the r port consists of input/output pins each addressed by 4 bits. input/output is controlled by the lar and lbr instructions and the lra and lrb instructions. the output data is stored in the port data register (pdr) of each pin. the on/off status of the output buffers is controlled by the r-port data control registers (dcr0?cr3: $030?033), which are mapped to memory addresses (figure 19). the r1 0 ?1 2 ports of the hd404394 series are n-channel middle-voltage open drain input/output pins. the r0 0 ?0 3 pins are also used as peripheral function pins: sck , si, so, and toc. setting of the peripheral functions for these pins is executed by bit 3 (smr3) of the serial mode register (smr:$005) and by bits 2 to 0 (pmra2?mra0) of port mode register a (pmra: $004), as shown in figures 21 and 22. the r3 0 ?3 3 pins of the hd404344r series and hd4074344 are also used as an 0 ?n 3 peripheral function pins. pins r3 1 ?3 3 of the hd404394 series are also used as an 1 ?n 3 peripheral function pins. the setting of peripheral functions for these pins is executed by bits 3 to 0 (amr13?mr10) of a/d mode register 1 (amr1: $019). for the hd404394 series, the use of amr10 is prohibited (figure 23). bit initial value read/write bit name 3 ? ? not used 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc figure 21 port mode register a (pmra)
hd404344r series/hd404394 series 47 bit initial value read/write bit name 3 0 w smr3 2 0 w smr2 0 0 w smr0 1 0 w smr1 serial mode register (smr: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smr2 smr0 smr1 smr3 0 1 r0 0 / sck mode selection r0 0 sck sck output output input clock source external clock ? prescaler division ratio see table 22. prescaler system clock figure 22 serial mode register (smr) bit initial value read/write bit name 3 0 w amr13 2 0 w amr12 0 0 w amr10 1 0 w amr11 amr10 * 0 1 an 0 a/d mode register 1 (amr1: $019) amr11 0 1 an 1 amr12 0 1 r3 2 /an 2 mode selection r3 2 an 2 amr13 0 1 r3 3 /an 3 mode selection r3 3 an 3 r3 0 /an 0 mode selection r3 0 r3 1 /an 1 mode selection r3 1 note: * available for the hd404344r series and hd4074344, but not available for the hd404394 series. figure 23 a/d mode register 1 (amr1)
hd404344r series/hd404394 series 48 pull-up mos transistor control pull-up mos, which can be controlled by software, is built into all input/output pins except r1 0 ?2 3 of the hd404394 series. the on/off status of all pull-up mos pins is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c) and the port data registers (pdr) of each pin. each pin can therefore independently switch between with or without pull-up mos (table 17 and figure 24). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 pmos on/off selection for pin r0 2 /so miscellaneous register (mis: $00c) 0 1 on off mis3 0 1 pull-up mos on/off selection pull-up mos off pull-up mos on programming mis1 and mis0 to 1 is prohibited. figure 24 miscellaneous register how to deal with unused i/o pins when input/output pins are not being used and are left floating, it is necessary to set these pins to v cc to reduce the possibility of lsi malfunctions due to noise. this can be done by selecting pull-up mos for the pins or by connecting an external pull-up resistor of about 100 k w at each unused pin.
hd404344r series/hd404394 series 49 prescaler the mcu has one built-in prescaler, s (pss). this divides the system clock and outputs the divided clock to the peripheral function modules as shown in figure 25. clocks for timers b and c except for external events, and clocks for serial interface except for the external clock are all selected from the prescaler output by programming each mode register. prescaler s is an 11-bit counter which inputs the system clock. after an mcu reset clears the prescaler to $000, it begins dividing the system clock. prescaler s stops operating due to either an mcu reset or stop mode. it cannot be stopped by any other mode. timer b timer c serial system clock prescaler s figure 25 prescaler output supply
hd404344r series/hd404394 series 50 timers the mcu has two built-in timers, b and c. the functions of each timer are listed in table 19. table 19 timer functions functions timer b timer c clock source prescaler s available available external event available timer functions free-running available available event counter available reload available available watchdog available timer output pwm available timer b timer b is an 8-bit multifunction timer that includes free-running, reload, and event counter features. these are described as follows. by setting timer mode register b1 (tmb1: $009), one of seven internal clocks supplied from prescaler s can be selected, or timer b can be used as an external event counter. by setting timer mode register b2 (tmb2: $026), timer b can be incremented by each edge detector of input signals at pin evnb. by setting timer write register bl, bu (twbl, twbu: $00a, $00b), timer counter b (tcb) can be written to during reload timer operation. by setting timer read register bl, bu (trbl, trbu: $00a, $00b), the contents of timer counter b can be read out. timer b operation free-running/reload timer operation: the selection of the free-running/reload timer, input clock source, and prescaler division ratio is done by timer mode register b1 (tmb1: $009). timer b is initialized to the data which is written to timer write register b (twbl: $00a, twbu: $00b) by software. the data is then incremented in steps of 1 by using the input clock. if the clock input is continued after timer b is set to $ff, an overflow occurs. timer b then begins counting again, setting the timer to the value in timer write register b (twbl: $00a, twbu: $00b) when the reload timer is selected, or reset to $00 when the free-running timer is selected.
hd404344r series/hd404394 series 51 the timer b interrupt request flag is set by an overflow. resetting the timer b interrupt request flag (iftb: $002, bit 0) is executed by either software or by an mcu reset. external event counter operation: by setting the external event input as an input clock source, timer b can operate as an external event counter. the d 0 / int 0 /evnb pins are set to be int 0 /evnb pins by port mode register b (pmrb: $024). the detection edge of the external event counter for timer b is selected as rising edge, falling edge, or rising/falling edge by timer mode register b2 (tmb2: $026). when the rising/falling edge is selected, the period must be set to more than 2t cyc between the falling edge and the rising edge. timer b is incremented by 1 using the edge selection in timer mode register b2 (tmb2: $026). other functions are based on the free-running/reload timer. timer counter b (tcb) ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 timer mode register b2 (tmb2) evnb selector system clock per prescaler s (pss) 2 edge detector edge detection control 3 timer write register b lower (twbl) timer mode register b1 (tmb1) timer write register b upper (twbu) clock free-running timer control timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register bu (trbu) overflow internal data bus figure 26 timer b free-running and reload operation block diagram
hd404344r series/hd404394 series 52 using timer b registers timer b sets the operation and the read/write data according to the following registers. ? timer mode register b1 (tmb1: $009) ? timer mode register b2 (tmb2: $026) ? timer write register b ? (twbl: $00a, twbu: $00b) ? timer read register b ? (trbl: $00a, trbu: $00b) ? port mode register b (pmrb: $024) timer mode register b1 (tmb1: $009): four-bit write-only register that selects the free-running/reload timer, input clock, and prescaler division ratio, as shown in figure 27. it is reset to $0 by an mcu reset. data written to timer mode register b1 is valid after two instruction cycles. the initial setting of timer b, which is set by writing to timer write register b (twbl: $00a, twbu: $00b), should be programmed only after a mode change has been effective. bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source d 0 / int 0 /evnb (external event tmb13 0 1 free-running/reload timer selection free-running timer reload timer input) figure 27 timer mode register b1 (tmb1)
hd404344r series/hd404394 series 53 timer mode register b2 (tmb2: $026): two-bit write-only register that sets the input edge detection of pin evnb, as shown in figure 28. it is reset to $0 by an mcu reset. bit initial value read/write bit name 3 ? ? not used 2 ? ? not used 0 0 w tmb20 1 0 w tmb21 timer mode register b2 (tmb2: $026) tmb21 0 1 tmb20 0 1 0 1 evnb edge detection selection no detection falling-edge detection rising-edge detection rising- and falling-edge detection figure 28 timer mode register b2 (tmb2) timer write register b (twbl: $00a, twbu: $00b): write-only register consisting of the lower digit (twbl) and the upper digit (twbu). the lower digit is reset to $0 by mcu reset, but the upper digit value cannot be guaranteed. see figures 29 and 30. timer b is initialized by writing to timer write register b (twbl: $00a, twbu: $00b). in this case, the lower digit (twbl) must be written to first, but writing only to the lower digit does not change the timer b value. timer b is initialized to the value in timer write register b at the same time the upper digit (twbu) is written to. when timer write register b is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer b. bit initial value read/write bit name 3 0 w twbl3 2 0 w twbl2 0 0 w twbl0 1 0 w twbl1 timer write register b (lower) (twbl: $00a) figure 29 timer write register b (lower) (twbl) bit initial value read/write bit name 3 undefined w twbu3 2 undefined w twbu2 0 undefined w twbu0 1 undefined w twbu1 timer write register b (upper) (twbu: $00b) figure 30 timer write register b (upper) (twbu)
hd404344r series/hd404394 series 54 timer read register b (trbl: $00a, trbu: $00b): read-only register consisting of the lower digit (trbl) and the upper digit (trbu) that holds the count of the timer b upper digit. see figures 31 and 32. the upper digit (trbu) must be read first. at this time, the count of the timer b upper digit is obtained, and the count of the timer b lower digit is latched to the lower digit (trbl). after this, by reading trbl, the count of timer b when trbu is read can be obtained. bit initial value read/write bit name 3 undefined r trbl3 2 undefined r trbl2 0 undefined r trbl0 1 undefined r trbl1 timer read register b (lower) (trbl: $00a) figure 31 timer read register b (lower) (trbl) bit initial value read/write bit name 3 undefined r trbu3 2 undefined r trbu2 0 undefined r trbu0 1 undefined r trbu1 timer read register b (upper) (trbu: $00b) figure 32 timer read register b (upper) (trbu) port mode register b (pmrb: $024): write-only register that selects the d 0 / int 0 /evnb pin as shown in figure 20. it is reset to $0 by an mcu reset.
hd404344r series/hd404394 series 55 timer c timer c is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are selected and described as follows. by setting timer mode register c (tmc: $00d), one of eight internal clocks supplied from prescaler s can be selected. by selecting pin toc with bit 2 (pmra2) of port mode register a (pmra: $004), timer c output (pwm output) is enabled. by setting timer write register cl, cu (twcl, twcu: $00e, $00f), timer counter c (tcc) can be written to. by setting timer read register cl, cu (trcl, trcu: $00e, $00f), the contents of timer counter c can be read out. an interrupt can be requested when timer counter c overflows. timer counter c can be used as a watchdog timer for detecting runaway programs.
hd404344r series/hd404394 series 56 timer counter c (tcc) ? 1024 ? 2048 port mode register a (pmra) selector ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 system clock per prescaler s (pss) 3 timer write register c lower (twcl) timer mode register c (tmc) timer write register c upper (twcu) clock free-running/ reload timer control timer read register c lower (trcl) interrupt request flag of timer c (iftc) timer read register cu (trcu) overflow toc timer output control timer output controller watchdog timer controller watchdog on flag (wdon) system reset signal internal data bus figure 33 timer c block diagram timer c operation free-running/reload timer operation: the selection of the free-running/reload timer, input clock source, and prescaler division ratio is done by timer mode register c (tmc: $00d). timer c is initialized to the data, which is written to timer write register c (twcl: $00e, twcu: $00f) by software. the data is then incremented in steps of 1 by using the input clock. if the clock input is continued after timer c is set to $ff, an overflow occurs. timer c then begins counting again, setting the timer to the value in timer write register c (twcl: $00e, twcu: $00f) when the reload timer is selected, or reset to $00 when the free-running timer is selected. the timer c interrupt request flag is set by an overflow. resetting the timer c interrupt request flag (iftc: $002, bit 2) is executed by either software or by an mcu reset.
hd404344r series/hd404394 series 57 watchdog timer operation: timer c can be used as a watchdog timer for programs that may run out of control. a watchdog timer is enabled when the setting on the watchdog on flag (wdon: $020, bit 1) is 1. when timer c overflows, an mcu reset occurs. this usually controls programs running out of control by initializing timer c through software before timer c counts up to $ff (figure 34). $ff + 1 $00 timer c count value overflow time cpu operation normal operation timer c clear normal operation timer c clear program runaway normal operation reset figure 34 watchdog timer operation flowchart timer output operation: timer c can select the timer output mode by selecting the toc pin after setting bit 2 (pmra2) of port mode register a (pmra: $004) to 1. the output of the toc pin is initialized to 0 by an mcu reset. pwm output is a pulse output function of variable duty. the output wave differs by the contents of timer mode register c and timer write register c, as shown in figure 35. t (n + 1) t 256 t t (256 ?n) tmc3 = 0 (free-running timer) tmc3 = 1 (reload timer) notes: t: input clock period supplied to counter. (the clock input source and system clock division ratio are determined by timer mode register c.) n: value in timer write register c. (when n = 255 ($ff), pwm output is fixed low.) figure 35 pwm output waveform
hd404344r series/hd404394 series 58 using timer c registers timer c sets the operation and the read/write data according to the following registers. ? timer mode register c (tmc: $00d) ? timer write register c (twcl: $00e, twcu: $00f) ? timer read register c (trcl: $00e, trcu: $00f) timer mode register c (tmc: $00d): four-bit write-only register that selects the free-running/reload timer, input clock, and prescaler division ratio, as shown in figure 36. it is reset to $0 by an mcu reset. the data written to timer mode register c is valid after two instructions cycles. the initial setting of timer c, which is set by writing to timer write register c (twcl: $00e, twcu: $00f), should be programmed to execute only after a mode change has been effective. bit initial value read/write bit name 3 0 w tmc3 2 0 w tmc2 0 0 w tmc0 1 0 w tmc1 timer mode register c (tmc: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc2 tmc0 tmc1 input clock period tmc3 0 1 free-running/reload timer selection free-running timer reload timer 1024t cyc figure 36 timer mode register c (tmc)
hd404344r series/hd404394 series 59 timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of a lower digit (twcl: $00e) and an upper digit (twcu: $00f), as shown in figures 37 and 38. the operation of this register is the same as that of timer write register b. bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower) (twcl: $00e) figure 37 timer write register c (lower) (twcl) bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper) (twcu: $00f) figure 38 timer write register c (upper) (twcu) timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of a lower digit (trcl: $00e) and upper digit (trcu: $00f), which allows the upper digit of timer c to be read directly (figures 39 and 40). the operation of this register is the same as that of timer read register b. bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower) (trcl: $00e) figure 39 timer read register c (lower) (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper) (trcu: $00f) figure 40 timer read register c (upper) (trcu)
hd404344r series/hd404394 series 60 notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 20. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 20 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request t (255 ?n) t (n + 1) timer write register updated to value n interrupt request t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request t t (255 ?n) t timer write register updated to value n interrupt request t t (255 ?n) t
hd404344r series/hd404394 series 61 serial interface the mcu has a one-channel 8-bit serial interface built in with the following features. one of 12 different internal clocks or an external clock can be selected as the transmit clock. the internal clocks include the six prescaler outputs divided by two and by four, and the system clock. during idle states, the serial output pin can be controlled as high or low output. transmit clock errors can be detected. an interrupt request can be generated when any errors occurred or data transfer has completed. internal data bus ? 2 ? 8 ? 32 ? 128 ? 512 ? 2048 port mode register c (pmrc) sck selector system clock per prescaler s (pss) idle controller 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 1/2 si so octal counter (oc) i/o controller transfer control signal figure 41 serial interface block diagram
hd404344r series/hd404394 series 62 serial interface operation selection and changing of serial interface operation mode: the available settings for port mode register a (pmra: $004) and the serial mode register (smr: $005) are shown in table 21. to change the operating mode or to initialize the serial interface, write to the serial mode register. the r0 0 / sck pin is controlled by writing data to serial mode register (smr: $005). the r0 1 /si and r0 2 /so pins are controlled by writing data to port mode register a (pmra: $004). table 21 serial interface operating modes smr pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode setting serial clock source: the transmit clock is set by writing to the serial mode register (smr: $005) and port mode register c (pmrc: $025). serial data setting: serial data is sent by writing to the serial data register (srl: $006 and sru: $007). serial data can then be obtained by reading the serial data register. serial data is shifted by the transmit clock. the output of the so pin is undefined until the first serial data is output after an mcu reset, or until the output level control is performed during an idle state. transfer control: serial interface operation is initiated by an sts instruction. the octal counter is reset by the sts instruction to 000 and then incremented by one by the rising edge of the transmit clock. if eight rising edges from the transmit clock is input or the serial data transfer is cut-off, the counter is reset to 000, the serial interrupt request flag (ifs: $003, bit 2) is set, and the serial data transfer stops. as for using the built-in prescaler output for the transmit clock, selection for the transmit clock frequency can be from 4t cyc to 8192t cyc by setting bits 2 to 0 (smr2?mr0) of the serial mode register (smr: $005) and bit 0 (pmrc0) of port mode register c (pmrc: $025). writing to these registers for the setting of the transmit clock is shown in table 22.
hd404344r series/hd404394 series 63 table 22 transmit clock selection (prescaler output) pmrc smr bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 100 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 100 ? 16 32t cyc 1 ? 48t cyc serial interface operating states: the serial interface has the following operating states shown in figure 42, both in external clock mode and internal clock mode. ? sts wait state ? transmit clock wait state ? transfer state ? continuous clock output (internal clock mode only) sts wait state: the serial interface is put into the sts wait state by an mcu reset (00, 10 in figure 42). while in this state, the serial interface is initialized and does not operate, even if a transmit clock is provided. if an sts instruction is executed while in this state (01, 11), the serial interface transfers to the transmit clock wait state. transmit clock wait state: transmit clock wait state period starts from when an sts instruction is executed until the first transmit clock falling edge. while in the transmit clock wait state, if the transmit clock is input (02, 12), the octal counter is incremented by the transmit clock, the data in the serial data register shifts, and the serial interface enters the transfer state. however, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). by writing to the serial mode register (smr: $005) (04, 14) while in the transmit clock wait state, the serial interface changes to the sts wait state. transfer state: the transfer state period starts from the first falling edge of the transmit clock to the eighth rising edge of the transmit clock. while in the transfer state, if an sts instruction is executed or eight pulses of the transmit clock is applied, the octal counter will reset to 000 and the state will change. if an sts instruction is executed (05, 15), the state changes to the transmit clock wait state. after the
hd404344r series/hd404394 series 64 eight pulses of the transmit clock, the state changes to the transmit clock wait state for the external clock mode (03). also, the state changes to the sts wait state for the internal clock mode (13). in the internal clock mode, the transmit clock stops after eight pulses of the transmit clock are output. while in the transfer state, if the serial mode register (smr: $005) (06, 16) is written to, the serial interface is initialized and the state changes to the sts wait state. after the transfer state has changed to another state, the octal counter is reset to 000 and the serial interrupt request flag (ifs: $003, 2) is set. continuous clock output state (internal clock mode only): continuous clock output state is the state in which only the transmit clock from the sck pin is output without data transfer. this can be done only while in internal clock mode. when the status of the 1 and 0 bits (pmra1, pmra0) of port mode register a (pmra: $004) is 00 while in transmit clock wait state, the state can be changed to continuous clock output state by enabling the transmit clock (17). by writing to the serial mode register (smr: $005) while in continuous clock output state (18), the state will change to the sts wait state. sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) trans fer state (octal counter = 000) mcu reset smr write sts instruction transmit clock 8 transmit clocks 03 or sts instruction 05 (ifs 1) ? smr write (ifs 1) ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) smr write sts instruction transmit clock sts instruction 15 (ifs 1) ? 8 transmit clocks 13 or smr write (ifs 1) 16 internal clock mode continuous clock output state (pmra 0, 1 = 0, 0) smr write note: refer to the operating states section for the corresponding encircled numbers. mcu reset ? 04 00 01 06 02 18 14 transmit clock 17 11 12 10 figure 42 serial interface state transitions
hd404344r series/hd404394 series 65 output level control during idle states: the output level of the so pin can be set during either sts wait state or transmit clock wait state by software. during idle states, the output level is controlled by writing to bit 1 (pmrc1) of port mode register c (pmrc: $025). an example of output level control during idle states is shown in figure 43. during transfer state, output level control cannot be executed. state mcu reset pmra write smr write pmrc write sck pin sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write smr write pmrc write sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode (input) instruction write srl, sru sts so pin ifs sck pin (output) instruction write srl, sru sts so pin ifs figure 43 example of serial interface operation sequence
hd404344r series/hd404394 series 66 transmit clock error detection (external clock mode): serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during data transfer. a transmit clock error of this type can be detected as shown in figure 44. if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (ifs: $003, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. after the transfer is completed and ifs is reset, writing to the serial mode register (smr: $005) changes the state from transfer to sts wait. at this time the serial interface is in the transfer state, and the serial interrupt request flag (ifs: $003, bit 2) is set again, and therefore the error can be detected. transfer completion (ifs 1) interrupts inhibited ifs 0 smr write ifs = 1? transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedure state sck pin (input) transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smr is written, ifs is set. flag set because octal counter reaches 000. flag reset at transfer completion. smr write ifs 12 3 45678 figure 44 transmit clock error detection
hd404344r series/hd404394 series 67 notes on use: initializing after writing to registers: if port mode register a (pmra: $004) is written to in the transmit clock wait state or transfer state, the serial interface should be reinitialized by writing to the serial mode register (smr: $005). serial interrupt request flag (ifs: $003, bit 2) set: for the serial interface, if the state is changed from transfer state to another by writing to serial mode register (smr:$005) or executing the sts instruction during the first low pulse of the transmit clock, the serial interrupt request flag (ifs: $003, bit 2) is not set. to set the serial interrupt request flag (ifs: $003, bit 2), a serial mode register (smr: $005) write or sts instruction execution must be programmed to be executed after confirming that the sck pin is at 1, that is, after executing the input instruction to port r0. registers for serial interface the serial interface operation is selected, and serial data is read and written using the following registers: serial mode register (smr: $005) port mode register c (pmrc: $025) serial data registers (srl: $006 and sru: $007) port mode register a (pmra: $004) miscellaneous register (mis: $00c) serial mode register (smra: $005): this register has the following functions (figure 45): r0 0 / sck pin function selection selection of transmit clock selection of prescaler division ratio serial interface initialization the write-only serial mode register is reset to $0 by an mcu reset. writing to the serial mode register discontinues the transmit clock input to the serial data registers (srl: $006 and sru: $007) and the octal counter. the octal counter is then reset to 000. if the serial mode register is written to during serial interface operation, data transfer will be cut off and the serial interrupt request flag (ifs: $003, bit 2) will be set. data in the serial mode register becomes effective after two instruction execution cycles from the time the serial mode register is written to. it is therefore necessary to program the sts instruction to be executed two cycles after the serial mode register is written to.
hd404344r series/hd404394 series 68 bit initial value read/write bit name 3 0 w smr3 2 0 w smr2 0 0 w smr0 1 0 w smr1 serial mode register (smr: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smr2 smr0 smr1 smr3 0 1 r0 0 / sck mode selection r0 0 sck sck output output input clock source external clock ? prescaler division ratio see table 22. prescaler system clock figure 45 serial mode register (smr) port mode register c (pmrc: $025): this register has the following functions: prescaler division ratio selection output level control during idle states port mode register c is a two-bit write-only register, which cannot be changed during data transfer. bit 0 (pmrc0) selects the prescaler division ratio. only this bit is reset to 0 by an mcu reset. bit 1 enables the output level control of the so pin during an idle state. the output levels at the pins are therefore changed when writing to bit 1 (pmrc1).
hd404344r series/hd404394 series 69 bit initial value read/write bit name 3 ? not used 2 ? not used 0 0 w pmrc0 1 undefined w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 output level control in idle states low level high level pmrc0 0 1 transmit clock division ratio prescaler output divided by 2 prescaler output divided by 4 figure 46 port mode register c (pmrc)
hd404344r series/hd404394 series 70 serial data register (srl: $006, and sru: $007): this register has the following functions (figures 47 and 48): transmission data write and shift receive data shift and read data written to the serial data registers is output from the so pin, lsb first, synchronously with the falling edge of the transmit clock. also, data from the si pin (from the lsb) is input synchronously with the rising edge of the transmit clock. reading or writing to the serial data register should be performed after data transfer. read/write operation to this register during data transfer does not guarantee valid data. the input/output timing chart for the transmit clock and the data are shown in figure 49. bit initial value read/write bit name 3 undefined r/w sr3 2 undefined r/w sr2 0 undefined r/w sr0 1 undefined r/w sr1 serial data register (lower) (srl: $006) figure 47 serial data register (srl) bit initial value read/write bit name 3 undefined r/w sr7 2 undefined r/w sr6 0 undefined r/w sr4 1 undefined r/w sr5 serial data register (upper) (sru: $007) figure 48 serial data register (sru) lsb msb 12 345 678 ttransmit clock serial output data serial input data latch timing figure 49 serial interface timing
hd404344r series/hd404394 series 71 port mode register a (pmra: 004): this register a has the following functions: r0 1 /si pin function selection r0 2 /so pin function selection port mode register a is a three-bit write-only register and reset to 0 by an mcu reset, as listed in figure 50. bit initial value read/write bit name 3 ? ? not used 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc figure 50 port mode register a (pmra) miscellaneous register the miscellaneous register (mis: $00c) has the following functions: control of r0 2 /so pin pmos pull-up mos on/off selection it is a two-bit write-only register and is reset to $0 by an mcu reset, as listed in figure 51.
hd404344r series/hd404394 series 72 bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 pmos on/off selection for pin r0 2 /so miscellaneous register (mis: $00c) 0 1 on off mis3 0 1 pull-up mos on/off selection pull-up mos off pull-up mos on programming mis1 and mis0 to 1 is prohibited. figure 51 miscellaneous register
hd404344r series/hd404394 series 73 a/d converter the mcu has a built-in a/d converter that uses a sequential comparison method with a register ladder. it can perform a digital conversion with 3 or 4 analog inputs at 8-bit resolution. the following describes the features of the a/d converter. a/d mode register 1 (amr1: $019) is used to select digital or analog ports (figure 53). a/d mode register 2 (amr2: $01a) is used to set the a/d conversion speed (figure 54). the a/d channel register (acr: $016) is used to select an analog input channel (figure 55). a/d conversion is started by setting the a/d start flag (adsf: $020, bit 2) to 1. after the conversion is completed, converted data is stored in the a/d data register, and at the same time, the a/d start flag is cleared to 0 (figure 56). by setting the i ad off flag (iaof: $021, bit 2) to 1, the current flowing through the resistance ladder can be cut off even in standby or active mode (figure 57). a/d data registers (adrl: $017, adru: $018) are read-only registers used to store the conversion result. (adrl: lower 4 bits, adru: upper 4 bits.) these registers cannot be cleared by a reset input. also, data in these registers are not guaranteed during the conversion period. after the conversion is completed, an 8-bit result is set to these registers and kept until the next conversion starts (figures 58, 59, and 60). notes on use: use the sem or semd instruction for writing to the a/d start flag (adsf). do not write to the a/d start flag during a/d conversion. data in the a/d data register during a/d conversion is undefined. since the operation of the a/d converter is based on the clock from the system oscillator, the a/d converter does not operate in stop mode. in addition, to save power dissipation while in a stop mode, all current flowing through the converter? resistance ladder is cut off. output signal level from other ports should be fixed during a/d conversion. the port data register (pdr) is initialized to 1 by an mcu reset. at this time, if pull-up mos is selected as active by bit 3 of the miscellaneous register (mis3), the port will be pulled up to v cc . when using a shared r port/analog input pin as an input pin, clear pdr to 0. otherwise, if pull-up mos is selected by mis3 and pdr is set to 1, a pin selected by bit 1 of the a/d mode register as an analog pin will remain pulled up.
hd404344r series/hd404394 series 74 i ad off flag (iaof) selector 4 a/d channel register (acr) a/d mode register 2 (amr2) a/d mode register 1 (amr1) a/d interrupt request flag (ifad) encoder a/d data registers (adru, l) a/d start flag (adsf) d/a v cc (v ref ) * 2 gnd operating mode signal (1 in stop mode) internal data bus + ? comp a/d controller r3 3 /an 3 r3 2 /an 2 r3 1 /an 1 (r3 0 /an 0 ) * 1 control signal for conversion time 4 notes: 1. 2. available for the hd404344r series and hd4074344. not available for the hd404394 series. connected to v cc for the hd404344r series and hd4074344. connected to v ref for the hd404394 series. figure 52 a/d converter block diagram
hd404344r series/hd404394 series 75 bit initial value read/write bit name 3 0 w amr13 2 0 w amr12 0 0 w amr10 1 0 w amr11 amr10 * 0 1 an 0 a/d mode register 1 (amr1: $019) amr11 0 1 an 1 amr12 0 1 r3 2 /an 2 mode selection r3 2 an 2 amr13 0 1 r3 3 /an 3 mode selection r3 3 an 3 r3 0 /an 0 mode selection r3 0 r3 1 /an 1 mode selection r3 1 note: * available for the hd404344r series and hd4074344, but not available for the hd404394 series. figure 53 a/d mode register 1 (amr1) bit initial value read/write bit name 3 ? not used 2 ? not used 0 0 w amr20 1 ? not used amr20 0 1 67 t cyc a/d mode register 2 (amr2: $01a) conversion time 34 t cyc figure 54 a/d mode register 2 (amr2)
hd404344r series/hd404394 series 76 bit initial value read/write bit name 3 0 w acr3 2 0 w acr2 0 0 w acr0 1 0 w acr1 a/d channel register (acr: $016) 0 0 0 0 1 0 1 analog input selection an 0 an 1 an 2 an 3 acr3 acr1 acr2 acr0 1 note: available for the hd404344r series and hd4074344, but not available for the hd404394 series. * * figure 55 a/d channel register (acr) bit initial value read/write bit name 3 ? ? not used 2 0 r/w adsf 0 ? ? not used 1 0 w wdon a/d start flag (adsf: $020, bit 2) refer to the description of timers wdon 0 1 a/d conversion completed a/d conversion started a/d start flag (adsf) figure 56 a/d start flag (adsf)
hd404344r series/hd404394 series 77 bit initial value read/write bit name 3 0 r/w rame 2 0 r/w iaof 0 ? not used 1 ? not used i ad off flag (iaof: $021, bit 2) refer to the description of operating modes rame 0 1 i ad i ad current flows i ad off flag (iaof) current is cut off figure 57 i ad off flag (iaof) 3210 3210 msb lsb bit 0 bit 7 result adru: $018 adrl: $017 figure 58 a/d data register bit initial value read/write bit name 3 0 r adrl3 2 0 r adrl2 0 0 r adrl0 1 0 r adrl1 a/d data register lower (adrl: $017) figure 59 a/d data register lower (adrl)
hd404344r series/hd404394 series 78 bit initial value read/write bit name 3 1 r adru3 2 0 r adru2 0 0 r adru0 1 0 r adru1 a/d data register upper (adru: $018) figure 60 a/d data register upper (adru)
hd404344r series/hd404394 series 79 pin description in prom mode the hd4074344 and the hd4074394 are prom versions of a ztat ? microcomputer. in prom mode, the mcu stops operating, thus allowing the user to program the on-chip prom. pin number mcu mode prom mode dp-28s/fp-28da fp-30d pin i/o pin i/o remarks 11r1 0 i/o a 5 i 22r1 1 i/o a 6 i 33r1 2 i/o a 7 i 44r1 3 i/o a 8 i 55r2 0 i/o a 9 i 66r2 1 i/o a 10 i 77r2 2 i/o a 11 i 88r2 3 i/o a 12 i 9 9 osc 1 i oe i 10 10 osc 2 o 11 11 gnd gnd 12 nc 12 13 r3 0 /an 0 or v ref i/o or v ref 2 13 14 r3 1 /an 1 i/o m 0 i 14 15 r3 2 /an 2 i/o x on i 15 16 r3 3 /an 3 i/o o 0 i/o 17 nc 16 18 v cc v cc 17 19 test i v pp i 18 20 reset i reset i 19 21 r0 0 / sck i/o o 1 i/o 20 22 r0 1 /si i/o o 2 i/o 21 23 r0 2 /so i/o o 3 i/o 22 24 r0 3 /toc i/o o 4 i/o 23 25 d 0 / int 0 /evnb i/o a 0 i 24 26 d 1 i/o a 1 i 25 27 d 2 i/o a 2 i 26 28 d 3 i/o a 3 i 27 29 d 4 / stopc i/o ce i 28 30 d 5 i/o a 4 i notes: 1. i/o: input/output pin, i: input pin, o: output pin 2. r3 0 /an 0 is for the hd404344r series and v ref for the hd404394 series in mcu mode.
hd404344r series/hd404394 series 80 programmable rom operation the hd4074344 and hd4074394 on-chip proms are programmed in prom mode. in prom mode, the mcu does not operate. it can be programmed like a standard 27256 eprom using a standard prom programmer and a socket adapter as shown in figure 61. table 23 lists the recommended prom programmers and socket adapters. since instructions of the hmcs400 series consists of 10 bits, the hmcs400 series microcomputers incorporate a conversion circuit to enable the use of a general-purpose prom programmer. by this circuit, an instruction is read or written to using two addresses, lower five bits and upper five bits. for example, if 4 kwords of on-chip prom are programmed by a general-purpose prom programmer, 8 kbytes of addresses ($0000?1fff) should be specified. control signals address bus data bus a 14 ,a 13 2 a 12 ? 0 o 4 ? 0 28-to-28-pin socket adapter 30-to-28 pin socket adapter prom programmer v cc gnd v pp a 14 ? 0 o 7 ? 0 o 7 ? 5 ce , oe a 12 ? 0 o 4 ? 0 hd4074344 hd4074394 v cc gnd v pp x on m 0 reset 3 figure 61 prom mode connections
hd404344r series/hd404394 series 81 table 23 prom programmer and socket adapter prom programmer maker type name data i/o unisite aval corp. pkw-3100 socket adapter package maker type name dp-28s hitachi hs4344ess01h fp-28da hs4344esp01h fp-30d hs4344esf01h programming and verification the hd4074344 and hd4074394 can be high-speed programmed without causing voltage stress or affecting data reliability. table 24 shows how programming and verification modes are selected. table 24 prom mode selection pin mode ce oe v pp o 0 ? 4 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedance precautions 1. addresses $0000 to $1fff should be specified if the prom is programmed by a prom programmer. if address $2000 or higher is accessed, the prom may not be programmed or verified correctly. note that the plastic package type devices cannot be erased and reprogrammed. set all data in unused addresses to $ff. 2. be careful of not using the wrong prom programmer or socket adapter, which may cause an overvoltage and damage the lsi. make sure that the lsi is firmly fixed onto the socket adapter, and that the socket adapter is firmly fixed to the programmer. 3. the prom should be programmed with v pp = 12.5 v. other proms use 21 v. if 21 v is applied to the hd4074344 or hd4074394, the lsi may become permanently damaged. 12.5 v is intel? 27256 v pp .
hd404344r series/hd404394 series 82 addressing modes ram addressing modes register indirect addressing mode: the contents of the w, x, and y registers (10 bits total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 digits from $040 to $04f, are accessed with the lamr and xmra instructions. rom addressing modes direct addressing mode: a program can branch to any address in rom memory space by executing the jmpl, brl, or call instruction. 30 30 0 0 0 9 9 1 w x y opcode register indirect addressing 2nd instruction word ram address direct addressing instruction 9 0 0 9 ram address 1st instruction word 3 7 30 memory register addressing 0 9 ram address 000100 opcode instruction figure 62 ram addressing modes
hd404344r series/hd404394 series 83 current page addressing mode: a program can branch to any address in the current page (256 words per page) by executing the br instruction. zero-page addressing mode: a program can branch to any subroutine located in the zero-page subroutine area ($0000?003f) by executing the cal instruction. table data addressing mode: a program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the b register by executing the tbr instruction. 0 0 direct addressing 2nd instruction word program counter current page addressing 97 0 9 program counter 1st instruction word 50 zero-page addressing 00 operand 0 9 table data addressing 7 13 0 9 operand opcode 3 0 13 operand ****** opcode program counter 0 13 3 operand opcode ba 0 9 opcode 00000000 program counter 0 13 figure 63 rom addressing modes
hd404344r series/hd404394 series 84 addressing mode for p instruction: by using the p instruction, the rom data determined by table data addressing can be referenced. the lower-order 8 bits of rom data are written in the accumulator and the b register when bit 8 of the rom data is 1, and are written in the r1 and r2 port output registers when bit 9 is 1. if bit 8 and bit 9 are both 1, the rom data is simultaneously written into the accumulator, the b register, and the r1 and r2 port output registers. (see figure 64.) the program counter is not affected by the p instruction. accumulator referenced rom address address b register 0 0 [p] instruction opcode ro 8 = 1 accumulator, b register rom data pattern output rom data ro 9 = 1 output registers r1, r2 p 3 p 2 p 1 p 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 ra 13 ra 12 ra 11 ra 10 ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ro 9 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 ro 9 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 figure 64 p instruction
hd404344r series/hd404394 series 85 br branching instruction at page boundary: when the br instruction is at a page boundary (256n + 255), the address in the program counter is transferred over to point to the next page as done by the internal hardware. therefore, executing the br instruction at a page boundary will cause the program to branch to the next page. (see figure 65.) br aaa aaa nop br aaa br bbb bbb nop 256 (n ?1) + 255 256n 256n + 254 256n + 255 256 (n + 1) figure 65 br instruction at page boundary
hd404344r series/hd404394 series 86 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v 2 ?.3 to +15.0 v 3 total permissible input current ? i o 100 ma 4 total permissible output current ? i o 30 ma 5 maximum input current i o 30 ma 6, 7 4 ma 6, 8 maximum output current ? o 4ma9 operating temperature t opr ?0 to +75 c10 storage temperature t stg ?5 to +125 c11 notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to pin test (v pp ) of the hd4074344 and hd4074394. 2. applies to the following pins. hd404344r series and hd4074344: d 0 ? 5 , r0, r1, r2, r3 hd404394 series: d 0 ? 5 , r0, r1 3 , r2, r3 1 ?3 3 3. applies to the following pins. hd404394 series: r1 0 ?1 2 4. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 5. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 6. the maximum input current is the maximum current flowing from each i/o pin to gnd. 7. applies to d 1 , d 2 , r1, and r2. 8. applies to the following pins. hd404344r series and hd4074344: d 0 , d 3 ? 5 , r0, r3 hd404394 series: d 0 , d 3 ? 5 , r0, r3 1 ?3 3 9. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 10. the operating temperature indicates the temperature range in which power can be supplied to the lsi (voltage vcc shown in the electrical characteristics tables can be applied). 11. in the case of chips, the storage specification differs from that of the package products. please consult your hitachi sales representative for details.
hd404344r series/hd404394 series 87 electrical characteristics dc characteristics (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition notes input high voltage v ih reset , sck , int 0 , stopc , evnb 0.8v cc ? cc + 0.3 v si 0.7v cc ? cc + 0.3 v osc 1 v cc ?0.5 v cc + 0.3 v input low voltage v il reset , sck , int 0 , stopc , evnb ?.3 0.2v cc v si ?.3 0.3v cc v osc 1 ?.3 0.5 v output high voltage v oh sck , so, toc v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck , so, toc 0.4 v i ol = 0.5 ma i/o leakage current |i il | reset , sck , si, so, toc, osc 1 , int 0 , stopc , evnb 1 m av in = 0 v to v cc 1 current dissipation in active mode i cc1 v cc 3.5 ma v cc = 5 v, f osc = 4 mhz 2 i cc2 0.4 ma v cc = 3 v, 2, 4 0.5 ma f osc = 400 khz 5 current dissipation in standby mode i sby1 v cc 1.5 ma v cc = 5 v, f osc = 4 mhz 3 i sby2 0.2 ma v cc = 3 v, 3, 4 0.4 ma f osc = 400 khz 3, 5 i sby3 0.6 ma v cc = 5 v, f osc = 800 khz 3, 5, 6
hd404344r series/hd404394 series 88 dc characteristics (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) (cont) item symbol pins min typ max unit test condition notes current dissipation in stop mode i stop v cc 10 m av in ( reset ) = v cc ?0.3 v to v cc , v in (test) = 0 to 0.3 v stop mode retaining voltage v stop v cc 2v notes: 1. excludes current flowing through pull-up mos and output buffers. 2. i cc is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset , test at gnd d 0 ? 5 , r0?3 at v cc 3. i sby is the source current when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset standby mode pins: reset at v cc test at gnd d 0 ? 5 , r0?3 at v cc 4. applies to the hd404394 series and hd4074344. 5. applies to the hd404344r series. 6. the current in case of excluding the current through a/d converters ladder resistance (flag i aof is set to ??. circuit structure and circuit constants of oscillator circuit is the following condition. circuit structure circuit constants osc1 osc2 rf rd c1 c2 ceramic oscillator ceramic oscillator: kbr-800ftr (kyosera) c1 = c2 = 100 pf r f = 1 m w r d = 2.2 k w
hd404344r series/hd404394 series 89 i/o characteristics for standard pins (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) pins item symbol hd404344r series, hd4074344 hd404394 series min typ max unit test condition note input high voltage v ih d 0 ? 5 , r0?3 d 0 ? 5 , r0, r1 3 , r2, r3 1 ?3 3 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 5 , r0?3 d 0 ? 5 , r0, r1 3 , r2, r3 1 ?3 3 ?.3 0.3v cc v output high voltage v oh d 0 ? 5 , r0?3 d 0 ? 5 , r0, r3 1 ?3 3 v cc ?1.0 v i oh = 0.5 ma ?1 3 , r2 v cc ?0.5 v 500 k w at v cc 2 output low voltage v ol d 0 ? 5 , r0?3 d 0 ? 5 , r0, r1 3 , r2, r3 1 ?3 3 0.4 v i ol = 0.5 ma d 1 , d 2 , r1, r2 d 1 , d 2 , r1 3 , r2 2.0 v i ol = 15 ma, v cc = 4.5?.5 v input leakage current |i il |d 0 ? 5 , r0?3 d 0 ? 5 , r0, r1 3 , r2, r3 1 ?3 3 1 m av in = 0 v to v cc 1 pull-up mos current ? pu d 0 ? 5 , r0?3 d 0 ? 5 , r0, r3 1 ?3 3 30 150 300 m av cc = 5 v, v in = 0 v notes: 1. output buffer current and pull-up mos current are excluded. 2. applies to the hd404394 series.
hd404344r series/hd404394 series 90 i/o characteristics for nmos intermediate-voltage pins for hd404394 series (v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition notes input high voltage v ih r1 0 ?1 2 0.7v cc 12.0 v 1 input low voltage v il r1 0 ?1 2 ?.3 0.3v cc v1 output high voltage v oh r1 0 ?1 2 11.5 v 500 k w at 12 v 1 output low voltage v ol r1 0 ?1 2 0.4 v i oh = 0.5 ma 1 r1 0 ?1 2 2.0 v i ol = 15 ma, v cc = 4.5 to 5.5 v 1 i/o leakage current |i il |r1 0 ?1 2 20 m av in = 0 v to 12 v 1, 2 notes: 1. applies to the hd404394 series. 2. excludes output buffer current. a/d converter characteristics (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note analog reference voltage v ref v ref 0.5v cc ? cc v2 analog input voltage av in an 0 ?n 3 gnd v cc v1 an 1 ?n 3 gnd v ref v2 current flowing between v ref and gnd i ad 200 m av ref = v cc = 5.0 v 2 analog input capacitance ca in an 0 ?n 3 ?5pf resolution 8 bit number of input channels 0 4 channel 1 0 3 channel 2 absolute accuracy an 0 ?n 3 ?.0 2.0 lsb 1 an 0 ?n 3 ?.5 2.5 lsb t a = 25 c, 2 an 1 ?n 3 ?.0 3.0 lsb v ref = v cc = 5.0 v 3 conversion time 34 67 t cyc input impedance an 0 ?n 3 1 m w f osc = 1 mhz, v in = 0 v notes: 1. applies to the hd404344r series. 2. applies to the hd4074344. 3. applies to the hd404394 series.
hd404344r series/hd404394 series 91 ac characteristics (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note clock oscillation frequency (ceramic oscillator) f osc osc 1 , osc 2 0.4 4.5 mhz division by 4 clock oscillation frequency (resistor oscillator) f osc osc 1 , osc 2 1.0 2.0 3.5 mhz division by 4 r f = 20 k w instruction cycle time (external clock, ceramic oscillator) t cyc 0.89 10 m s division by 4 instruction cycle time (resistor oscillator) t cyc 1.14 4.0 m s division by 4 r f = 20 k w oscillation setting time (external clock) t rc osc 1 , osc 2 2 ms 1 oscillation setting time (ceramic oscillator) t rc osc 1 , osc 2 2 ms 1 oscillation setting time (resistor oscillator) t rc osc 1 , osc 2 0.5 ms r f = 20 k w 1, 11 external clock high-level width t cph osc 1 92ns 2 external clock low-level width t cpl osc 1 92ns 2 external clock rise time t cpr osc 1 20ns 2 external clock fall time t cpf osc 1 20ns 2 int 0 , evnb high-level width t ih int 0 , evnb 2 t cyc 3 int 0 , evnb low-level width t il int 0 , evnb 2 t cyc 3 reset low-level width t rstl reset 2 t cyc 4 stopc low-level width t stpl stopc 1 t rc 5 reset rise time t rstr reset 20ms 4 stopc rise time t stpr stopc 20ms 5
hd404344r series/hd404394 series 92 ac characteristics (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) (cont) item symbol pins min typ max unit test condition note input capacitance c in all input pins except test, v ref and r1 0 ?1 2 15 pf f = 1 mhz, v in = 0 v test 15 pf f = 1 mhz, v in = 0 v 6 40pf 7 v ref 30pf 8 r1 0 ?1 2 15pf 9 30pf 10 notes: 1. the oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. after v cc reaches the minimum specification value at power-on. b. after reset input goes low when stop mode is cancelled. c. after stopc input goes low when stop mode is cancelled. to ensure the oscillation stabilization time at power-on or when stop mode is cancelled, reset or stopc must be input for at least a duration of t rc . when using a ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. refer to figure 66. 3. refer to figure 67. 4. refer to figure 68. 5. refer to figure 69. 6. applies to the hd404341r, hd404342r, hd404344r, hd404391, hd404392, and hd404394. 7. applies to the hd4074344 and hd4074394. 8. applies to the hd404394 series. 9. applies to the hd404344r series. 10. applies to the hd404394 series and hd4074344. 11. applies to the hd40c4344r, hd40c4342r, hd404341r
hd404344r series/hd404394 series 93 serial interface timing characteristics (hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, hcd404344r, hcd40c4344r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = +75 c, hd404394, hd404392, hd404391, hd4074344, hd4074394: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pins test condition min typ max unit note transmit clock cycle time t scyc sck load shown in figure 71 1 t cyc 1 transmit clock high width t sckh sck load shown in figure 71 0.4 t scyc 1 transmit clock low width t sckl sck load shown in figure 71 0.4 t scyc 1 transmit clock rise time t sckr sck load shown in figure 71 80ns1 transmit clock fall time t sckf sck load shown in figure 71 80ns1 serial output data delay time t dso so load shown in figure 71 300 ns 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 during transmit clock input item symbol pins test condition min typ max unit note transmit clock cycle time t scyc sck 1 t cyc 1 transmit clock high width t sckh sck 0.4 t scyc 1 transmit clock low width t sckl sck 0.4 t scyc 1 transmit clock rise time t sckr sck 80ns1 transmit clock fall time t sckf sck 80ns1 serial output data delay time t dso so load shown in figure 71 300 ns 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. refer to figure 70.
hd404344r series/hd404394 series 94 v ?0.5 v cc 0.5 v osc 1 t cph t cpl 1/f cp t cpf t cpr figure 66 external clock timing 0.8v cc 0.2v cc int 0 , evnb t il t ih figure 67 interrupt timing reset t rstr t rstl 0.2v cc 0.8v cc figure 68 reset timing t stpr t stpl 0.8v cc 0.2v cc stopc figure 69 stopc timing
hd404344r series/hd404394 series 95 0.7v cc 0.3v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?0.5 v cc v ?0.5 v (0.8v ) * cc 0.4 v (0.2v ) * sck so si note: * v cc ?0.5 v and 0.4 v are the threshold voltages for transmit clock output, and 0.8v cc and 0.2v cc are the threshold voltages for transmit clock input. cc cc t sckh figure 70 serial interface timing r l = 2.6 k w v cc hitachi 1s2074 h or equivalent r = 12 k w test point c = 30 pf figure 71 timing load circuit
hd404344r series/hd404394 series 96 1 0.0 0.5 1.0 1.5 2.0 i cc (ma) v cc (v) 23456 ta = 25 c, f cyc = f osc /4 sample: typ (a) i cc vs v cc characteristics (ceramic oscillator) f osc = 4 mhz f osc = 2 mhz f osc = 1 mhz f osc = 800 khz f osc = 400 khz 1 0.0 1.0 0.5 1.5 2.0 2.5 i cc (ma) v cc (v) 23456 (b) i cc vs v cc characteristics (resistor oscillator) ta = 25 c, r f = 20 k f cyc = f osc /4 sample: typ 1 f osc (mhz) v cc (v) 23456 (c) f osc vs v cc characteristics (resistor oscillator) 0 0.0 2.0 1.0 3.0 4.0 5.0 1.0 2.0 1.5 2.5 3.0 3.5 f osc (mhz) r f (k ) 10 20 30 40 50 (d) f osc vs r f characteristics (resistor oscillator) ta = 25 c, sample: typ ta = 25 c, r f = 20 k sample: typ 0 v ol (v) i ol (ma) 10 20 30 40 50 (e) v ol vs i ol characteristics (d 1 , d 2 , r1, r2 pins) 0.0 1.0 0.5 1.5 2.0 2.5 ta = 25 c sample: typ v cc = 5 v v cc = 3.5 v v cc = 2.5 v v cc = 4.5 v v cc = 5 v v cc = 5.5 v figure 72 characteristics curve hd404344r series (consultation value)
hd404344r series/hd404394 series 97 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as 4-kword versions (hd404344r and hd404394). a 4-kword data size is required to change rom data to mask manufacturing data since the program used is for a 4-kword version. this limitation apply to the case of using eprom and the case of using data base. $0000 $000f $0010 $003f $0040 $03ff $0400 $0fff rom 1 kwords version: hd404341r, hd40c4341r, hd404391 address $0400 to $0fff vector address zero page subroutine (64 words) pattern and program (1,024 words) rom 2 kwords version: hd404342r, hd40c4342r, hd404392 address $0800 to $0fff fill this area with all 1s not used $0000 $000f $0010 $003f $0040 $07ff $0800 $0fff vector address zero page subroutine (64 words) pattern and program (2,048 words) not used
hd404344r series/hd404394 series 98 hd404341r/hd404342r/hd404344r/hcd404344r/hd40c4341r/hd40c4342r/ hd40c4344r/hcd40c4344r option list 2. rom code media date of order customer department name rom code name lsi number eprom: ceramic oscillator external clock rc oscillator hd404341r/hd404342r/hd404344r/hcd404344r hd40c4341r/hd40c4342r/hd40c4344r/hcd40c4344r f = mhz f = mhz 3. system oscillator (osc1?sc2) (shaded areas indicate selections that are not available.) the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. hd404341r hd404342r hd404344r hcd404344r 1. rom size dp-28s fp-28da fp-30d chip 5. package type note: the specifications of shipped chips differ from of the package product. please contact our sales staff for details. 1-kword 2-kword 4-kword 4-kword ceramic oscillator external clock hd404341r hd404342r hd404344r hcd40c4344r 1-kword 2-kword 4-kword 4-kword rc oscillator please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). please check off the appropriate applications and enter the necessary information. used not used 4. stop mode
hd404344r series/hd404394 series 99 hd404391/hd404392/hd404394 option list date of order customer department name rom code name lsi number eprom: ceramic oscillator external clock f = mhz f = mhz 3. system oscillator (osc1?sc2) the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 2. rom code media hd404391 hd404392 hd404394 1. rom size 1-kword 2-kword 4-kword please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). dp-28s fp-28da fp-30d 5. package type used not used 4. stop mode please check off the appropriate applications and enter the necessary information.
hd404344r series/hd404394 series 100 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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